In the past, alternate ways for determining the reliability of semiconductor chips or test specimens, (microcircuit die in their bare, non-incapulated form) have been used in modern military and space applications. Under conventional chip testing, reliability is determined using two industry standard procedures: (a) wafer probing where an array of chips on a wafer are probed at room temperature; and (b) statistical sampling with thermal stress.
Wafer probing technology has been the accepted way for chip testing where the microelectronic devices are electrically tested at room temperature. A wafer is usually four or five inches in diameter and contains and array of several chips of the same type. After probing, the wafer is scribed (cut) and separated and the individual chips are then available for use on the production floor. Wafer probing is a static test, meaning electrical continuity between critical circuit paths are verified, but total electrical function is not determined due to time constraints and associated cost. Thermal screening is not technically feasible since there is not a thermal forcing technique available that can rapidly cycle the large mass of a four or five inch wafer. Therefore, chip integrity is still questionable after wafer probing and damage incurred during the scribing process is evaluated only by visual inspection.
Statistical sampling is another industry accepted chip testing practice used to determine complete electrical functions and operating reliability, including MIL-SPEC temperature ranges. Under this methodology, one to two percent of the individual chips are separated from the wafer and mounted into a custom test fixture and subjected to dynamic electrical and thermal evaluation. Based upon the compiled test results, predictions are made concerning the other 98 to 99 percent of chips. And the chips which are used for test purposes are not usable after mounting in the test fixture.
Therefore, for the most part, chip reliability is unknown until they are assembled into the final electrical package (usually a Hybrid Microelectronic Assembly (HMA) which is used extensively in military and space applications), and the completed HMA package is subjected to MIL-SPEC final test. At this point in the manufacturing process non-functional HMA packages must undergo labor intensive troubleshooting to determine the cause of failure, and faulty chips must be removed and replaced per MIL-SPEC procedures. In many cases the cost of repairing a faulty HMA package exceeds the cost of producing the entire package.
Accordingly, it is an object of this invention to provide a test procedure that is economical enough that each semiconductor chip can be tested before assembling into a larger assembly such as a HMA.
Another object of this invention is to provide a system for testing semiconductor chips that enables the chip to be tested not only electrically but also under varied thermal conditions.
Still another object of this invention is to provide a system that enables a semiconductor chip to be tested both electrically and when the chip is in a pre-determined thermal condition.
Still another object of this invention is to provide a thermal screening system that can be used to satisfy military requirements as well as space industrial requirements.
Yet another object of this invention is to provide a system that is able to perform concurrent electrical/thermal testing of bare, individual semiconductor chips.
Still another object of this invention is to provide a system in which the electrical probing is of the nondestructive type.
Other objects and advantages of this invention will be obvious to those skilled in this art.